Field of the Invention
Embodiments of the present invention relate to tools for the automated simulation of computer hardware.
Related Art
During the design of a microprocessor, or microcontroller, it is generally necessary to specify an instruction set that describes the instructions to be performed or executed by the processor. It is generally desirable to test such an instruction set prior to the actual manufacture of a hardware embodiment of the microprocessor. A software tool that enables such testing of instructions is generally known or referred to as an instruction set simulator.
Conventional instruction set simulators are generally undesirably slow. Generally, such a simulator executes a description of the instruction behavior, e.g., as specified by the processor designer, for every instruction. For example, two different instructions of the same type, e.g., “ADD R1, R2, R3” and “ADD R5, R6, R7,” are generally simulated by executing exactly the same instruction description.
In a case in which a high level description of an instruction contains control structures, for example, “if/then/else” structures, the conventional art generator typically generates host simulation instruction for all possible outcomes of the control structure. If control structures are nested, as is common, this process can result in creation of very large numbers of code segments corresponding to all possible permutations of test conditions.
As an unfortunate result, conventional simulation can execute hundreds to thousands of times slower than a target set of instructions is designed to operate.